LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

PACKAGE p_alu IS

	COMPONENT logic_unit IS
	PORT(	a: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			sel: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
			y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
	END COMPONENT;
	
	COMPONENT arith_unit IS
	PORT(	a: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			sel: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
			cin: IN STD_LOGIC;
			y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
	END COMPONENT;
	
	COMPONENT mux IS
	PORT(	a: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			sel: IN STD_LOGIC;
			y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
	END COMPONENT;

	
END p_alu;

